1. Field of the Invention
The present invention relates to the fabrication of multi-layer, interconnected substrates for semiconductor devices, and more specifically, to a method of fabricating a substrate having a conductive layer on each side, with the two conductive layers interconnected by a conductive via.
2. Description of the Prior Art
Double-sided and multi-layer printed circuit boards are now commonly used in the semiconductor industry to increase the density of integrated circuits. Such circuit boards are typically formed from a planar dielectric substrate having printed circuitry on each side. The conductive layers on the surfaces of the substrate are interconnected by conductive vias formed through the substrate. Multiple substrates of this kind may be stacked and interconnected to form more complex structures.
Conventionally, an interconnection between the conductive layers on the opposing surfaces of a dielectric substrate is formed by first etching a via in the dielectric substrate. A vacuum deposition or electroless plating operation is then performed to form a thin metal layer on one or both sides of the substrate. An electrical deposition process is then used to fill the via and plate the side(s) of the substrate with a metal layer of desired thickness.
However, this conventional method has several disadvantages. A vacuum deposition step is expensive to implement because of the cost of the equipment needed and the comparatively low throughput. Electroless plating operations suffer from poor adhesion of the metal layer to the substrate and small thickness of the plated metal.
Another conventional method of forming a dielectric substrate having a double sided conductive layer which is interconnected by a conductive via is to prepare the double sided substrate and then form a via hole. The via hole is then filled and connected to the two conductive layers by a metallization step. However, the via hole coating is limited in thickness by the patterned metal layer thickness because the same process step is used to fill the via hole and plate the pad(s) and trace patterns.
What is desired is a method of fabricating a substrate having a conductive layer on opposing sides, with the conductive layers interconnected by a conductive via, which overcomes the disadvantages of the conventional approaches to fabricating such a structure.
The present invention is directed to a method of fabricating a substrate having a conductive layer on opposing sides, with the conductive layers interconnected by a conductive via. The inventive method uses a dielectric substrate having a conductive layer deposited or laminated onto one or both of the substrate""s opposing surfaces. For the situation of a metal layer on one side of the substrate, a laser drill may be used to drill blind vias through the dielectric, stopping at the substrate/conductive layer interface. An electrolytic plating process is used to fill the via by establishing an electrical connection to the conductive layer. A second conductive layer may be deposited or laminated to the other surface of the substrate. If the starting structure has a conductive layer on both sides of the substrate, the drill is controlled to bore through the upper conductive layer and then drilling is continued at a lower power through the substrate. The blind vias drilled through the upper conductive layer will be plated during the via filling stage, and may be planarized, if desired, to provide a planar surface between the filled via sites and the surrounding conductive layer. The conductive layer(s) may then be patterned as desired to form pads and interconnection traces.